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ADP3120A
OD
3
V CC
TSD
1
BST
UVLO
IN
2
8
DRVH
FALLING
EDGE
DELAY
MONITOR
7
SWN
FALLING
EDGE
DELAY
MONITOR
START STOP
MIN DRVL
OFF TIMER
NON ? OVERLAP
TIMERS
4
5
6
V CC
DRVL
PGND
Figure 1. Block Diagram
PIN DESCRIPTION
SO ? 8
1
DFN8
1
Symbol
BST
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high ? side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0 m F. An external diode is required with the ADP3120A.
2
3
4
5
6
7
8
2
3
4
5
6
7
8
IN
OD
V CC
DRVL
PGND
SWN
DRVH
Logic ? Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0 m F ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
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